1. Field of the Invention
This invention relates to electrical components that are mounted on printed circuit (PC) boards using a ball grid array (BGA) and more specifically to relieving stress on the ball joints caused by thermal coefficient of expansion (TCE) mismatch between the electrical component and the printed circuit (PC) board.
2. Description of the Related Art
Historically, integrated circuits (ICs) have been mounted on leadframes and packaged in ceramic or plastic materials with the fingers, e.g. leads, of the leadframes extending out of the sides of the package. The most common package is a Dual-in-line package (DIP), which is rectangularly shaped with an equal number of leads extending from both sides. Quad packages are typically square and have leads distributed around their circumference. Ceramics are usually used for state-of-the art devices, where reliability and a hermitic seal are required. Plastics are usually better for more mature commercial products where cost is paramount and hermeticity is not required.
The packaged ICs are surface mounted onto PC boards by soldering their leads onto contact pads. The leads are typically soldered by screen-printing solder paste onto the contact pads, attaching the package, and then reflowing the solder by vapor phase, infra-red, or wave reflow. The contact pads are connected through traces on the multi-layer PC board to other ICs or circuitry.
As very large scale integration (VLSI) technology advances, the IC device-size shrinks and the lead count grows. Using conventional packaging techniques, the space required for interconnection becomes a major fraction of the chip area, which in turn reduces the available space for the active device. To overcome this problem, packaged ICs and unpackaged flip-chip devices 10 are fabricated with a ball grid array (BGA) 12 on their bottom surfaces to provide I/O interconnections for circuitry 14 as shown in FIG. 1. The BGAs are aligned with the contact pads 16 of the PC board 18 and reflow soldered. This approach increases both the number of leads per package and the size of the active device.
Although the use of BGAs overcomes the I/O problem between the ICs and the PC board, the solder joints between the BGA and the package and between the BGA and the PC board are more susceptible to thermal coefficient of expansion (TCE) mismatch than the conventional surface mounting techniques. When undergoing thermal cycling, the TCE mismatch between the PC board and the package produces stress on the solder joints. This stress causes microcracks to appear in the joints, which eventually causes them to fail.
Plastic packages used in commercial products exhibit TCEs close to that of a standard epoxy-based PC board, which is approximately 17 parts per million (ppm). As a result, plastic packages, on average, routinely withstand 4-5 thousand thermal cycles between -40.degree. C. and 125.degree. C. prior to failure of a single interconnection. Conversely, ceramic packages exhibit a TCE of approximately 7 ppm. The amount of stress produced by this mismatch would reduce the reliability to approximately 100 thermal cycles, which is unacceptable.
Several different techniques have been tried to improve the reliability of ceramic packages. First, crack resistant alloys have been developed. However, these alloys only improve reliability to 200-400 cycles. Second, solder columns that are 3-4 times taller than the solder balls have been used. This allows the joints to flex and absorb some of the stress so that the package can withstand approximately 1000 thermal cycles. However, the solder columns are very fragile and susceptible to breakage during packaging. Lastly, the PC boards have been fabricated with a metal core to reduce the TCE mismatch. However, these boards are very expensive to produce and difficult to reflow solder. Ceramic boards may be used but they are limited in size and also very expensive. As a result, BGA attachment of ceramic packages has been abandoned in favor of the more reliable surface mounting technology.
Flip-chip devices also have a very low TCE, approximately 4.7 ppm for silicon based devices. To absorb the stress caused by the mismatch, a liquid adhesive is wicked around the solder bumps via capillary action to underfill the flip-chip device. The adhesive must be thin enough to flow easily but not leave voids. Furthermore, the curing temperature cycle stresses the flip-chip device reducing its reliability. Note, underfilling cannot be used with ceramic packages because the spacing between the package and the PC board is too great to provide adequate capillary action.